Formal Verification Engineer

NVIDIA is hiring Formal Verification Engineers for its Hardware Team. The company is focused on advancing parallel computing, AI, graphics, and next-generation technologies that power industries ranging from gaming and robotics to autonomous vehicles and intelligent systems. This role offers an opportunity to work on innovative hardware technologies and contribute to building reliable, high-performance computing platforms used worldwide. Engineers in this team collaborate on complex verification challenges, helping ensure the quality and functionality of cutting-edge semiconductor designs. The ideal candidate is passionate about technology, problem-solving, and hardware verification, with a strong interest in shaping the future of AI-driven and accelerated computing solutions. NVIDIA provides a fast-paced, collaborative environment where creativity, technical excellence, and innovation are highly valued.

Gain hands-on experience with advanced formal verification techniques and modern verification practices. Apply industry-standard formal verification methodologies to validate complex digital designs, IPs, and SoCs. Take end-to-end ownership of verification activities by creating comprehensive verification and validation plans. Work closely with design and development teams to execute verification strategies effectively. Collaborate with cross-functional verification teams to achieve successful verification closure and ensure design quality.

B.Tech./ M.Tech in Electrical Engineering / Computer Science or related fields

1. Abstraction Techniques for Verification What is abstraction in formal verification Data abstraction and localization reduction Cone of influence reduction Counter-example guided abstraction refinement (CEGAR) Black box vs white box abstraction Property-driven abstraction Assume-guarantee reasoning Difference between simulation-based and formal verification Model checking basics (bounded & unbounded) State space explosion problem and how abstraction solves it 2. HDL — Verilog / SystemVerilog Verilog fundamentals (modules, ports, data types, operators) Blocking vs non-blocking assignments Always blocks (combinational vs sequential) Finite State Machine (FSM) coding (Mealy & Moore) SystemVerilog enhancements (logic, bit, enum, struct, union) Interfaces and modports SystemVerilog testbench basics (class, randomization, constraints) Functional coverage and covergroups UVM basics (if mentioned in JD or interview level) Common coding mistakes and synthesis vs simulation mismatch 3. RTL Understanding & Analysis How to read and trace RTL code quickly Identifying combinational vs sequential logic from code Understanding clock domains and reset schemes Datapath vs control path identification RTL to gate-level mapping concepts Pipelining and handshake protocols in RTL FIFO, arbiter, encoder, decoder, MUX — common RTL blocks Timing diagrams from RTL behavior Lint checks and common RTL issues Reading and interpreting waveforms from RTL simulation 4. Temporal Logic Assertions What are assertions and why they matter Immediate assertions vs concurrent assertions SystemVerilog Assertion (SVA) syntax and structure Sequences and properties in SVA Temporal operators — ##, |->, |=>, throughout, within Repetition operators — [*N], [->N], [=N] LTL (Linear Temporal Logic) basics — always, eventually, until, next CTL (Computation Tree Logic) overview Writing assertions for common protocols (handshake, FIFO full/empty, valid-ready) Cover properties vs assert properties Assertion failures — debugging and interpreting

1st Round : Written Test 2nd and 3rd Round : Technical Interview 4th Round : HR round